CPU 6510 / 8500

Employed in: C64, SX64, 1551 (6510T)

The 6510/8500 CPU (Central Processing Unit) (or MPU (Micro Processing Unit?)) is an 8-bit processor for the C64 and the SX64.

Technical data

0.9852484444MHz [1] (PAL)
1.0227277143MHz [1] (NTSC)
8 bit data bus
16 bit address bus
6 bit I/O port

Pinout

Fig. 1: 6510

Signal Description

(Click here for ASCII version)

Pin(s) Signal Dir Description
1 ø 0 in^* in Phi 0 in. The system clock signal, which is generated by the VIC-II in the C64, is applied to this input. In the C64, it is about 1MHz.
2 RDY in ReaDY. When going LOW, the CPU waits after next read cycle for this line going HIGH again.
3 /IRQ in Interrupt ReQuest. When going LOW, the CPU loads the PC with the value stored in $fffe / $ffff after processing the current command. This procedure will be executed only when interrupts have been enabled (bit 2 in flag register = 0).
Note that the IRQ signal must be applied until the CPU has checked this pin; a short IRQ pulse is not sufficient [2].
In the C64, there are three possible sources for an IRQ:

VIC-II, pin 8 (rasterline, lightpen, etc.)
CIA #1 (timer)
Expansion port, pin 4

4 /NMI in Non Maskable Interrupt. When going LOW, the CPU loads the PC with the value stored in $fffa / $fffb after processing the current command.
In the C64, there are three possible sources for an NMI:

RESTORE key
CIA #2
Expansion port, pin D

5 AEC in Address Enable Control. When going LOW, the CPU puts its bus lines into 'tri-state' mode and is thus totally decoupled from the rest of the system, so that another chip can take control over it.
6 V_cc - Supply voltage. This pin is connected to +5V DC.
7-20 A0-A13 in / out Address bus. The CPU applies the address of the next datum to be read or written.
21 GND - GrouND. (0V)
22-23 A14-A15 in / out Address bus. The CPU applies the address of the next datum to be read or written.
24-29 P5-P0 in / out Processor Port. With these lines, you can control RAM / ROM switching and the Datassette. See below (Programming info) for details.
30-37 D7-D0 in / out Data bus.
38 R/-W out Read/-Write. With this line, the CPU controls whether the next DRAM access will be a read or write cycle. LOW=write, HIGH=read. Note that all accesses only take place when ø2 is HIGH.
39 ø2 out^* out Phi2 out. The CPU outputs the system clock for the rest of the chips for synchronization.
40 /RES in RESet. When going LOW, the CPU resets and waits for a LOW-HIGH transistion to load the PC with the value stored in $fffc/$fffd. After power-up, timer A in the NE556 in the C64 pulls this line to LOW for a short time and half a second later back to HIGH.

^* The 'ø' is used as Greek 'phi' here.

Pin(s)	Signal	Dir	Description
1	ø 0 in^*	in	Phi 0 in. The system clock signal, which is generated by the VIC-II in the C64, is applied to this input. In the C64, it is about 1MHz.
2	RDY	in	ReaDY. When going LOW, the CPU waits after next read cycle for this line going HIGH again.
3	/IRQ	in	Interrupt ReQuest. When going LOW, the CPU loads the PC with the value stored in $fffe / $ffff after processing the current command. This procedure will be executed only when interrupts have been enabled (bit 2 in flag register = 0). Note that the IRQ signal must be applied until the CPU has checked this pin; a short IRQ pulse is not sufficient [2]. In the C64, there are three possible sources for an IRQ: VIC-II, pin 8 (rasterline, lightpen, etc.) CIA #1 (timer) Expansion port, pin 4
4	/NMI	in	Non Maskable Interrupt. When going LOW, the CPU loads the PC with the value stored in $fffa / $fffb after processing the current command. In the C64, there are three possible sources for an NMI: RESTORE key CIA #2 Expansion port, pin D
5	AEC	in	Address Enable Control. When going LOW, the CPU puts its bus lines into 'tri-state' mode and is thus totally decoupled from the rest of the system, so that another chip can take control over it.
6	V_cc	-	Supply voltage. This pin is connected to +5V DC.
7-20	A0-A13	in / out	Address bus. The CPU applies the address of the next datum to be read or written.
21	GND	-	GrouND. (0V)
22-23	A14-A15	in / out	Address bus. The CPU applies the address of the next datum to be read or written.
24-29	P5-P0	in / out	Processor Port. With these lines, you can control RAM / ROM switching and the Datassette. See below (Programming info) for details.
30-37	D7-D0	in / out	Data bus.
38	R/-W	out	Read/-Write. With this line, the CPU controls whether the next DRAM access will be a read or write cycle. LOW=write, HIGH=read. Note that all accesses only take place when ø2 is HIGH.
39	ø2 out^*	out	Phi2 out. The CPU outputs the system clock for the rest of the chips for synchronization.
40	/RES	in	RESet. When going LOW, the CPU resets and waits for a LOW-HIGH transistion to load the PC with the value stored in `$fffc/$fffd`. After power-up, timer A in the NE556 in the C64 pulls this line to LOW for a short time and half a second later back to HIGH.

Technical info

The 6510 is the 6502's successor, built into the C64, the SX-64, and some other 8-bit machines.
When introducing the new C-64s (flat case), Commodore replaced the 6510 by the 8500, which is fully compatible [3].

The 6510T is used in the 1551 disk drive. The Commodore Trivia #8 states:

It is a slight variant on the 6510 microprocessor used on the C64. Some say it runs at 2 MHz, but the specs drives spec sheet doesn't say.

So, if anyone knows more about the 6510T, please MAIL me!

Programming info

As opposed to the 6502, the 6510 MPU has an integrated 6 bit I/O port, which is used for the memory configuration and for controlling the datassette. The Data Direction Register at address $0000 controls whether the Peripheral Data Register port bits at address $0001 are inputs or outputs. If Bit 3 of the Date Direction Register is 1, then Bit 3 of the Peripheral Data Register is configured as output, whereas it would be configured as input if bit 0 in the Data Direction Register was 0. The individual bits of the Peripheral Data Register have the following functions:

P0: LORAM. If set to 1 (default), the BASIC ROM is mapped into $a000-bfff, if set to 0, accesses to this area address the RAM.
P1: HIRAM. If set to 1 (default), the KERNAL ROM is mapped into $e000-ffff, if set to 0, accesses to this area address the RAM. Alas, this bit also controls the mapping of the BASIC ROM, i.e. if the KERNAL ROM is deactivated, the BASIC ROM is deactivated, too. This means if you want to modify the KERNAL, you have to not only copy the KERNAL from ROM to RAM, but the BASIC ROM, too, since you cannot switch off the KERNAL ROM individually.
P2: CHAREN. Setting this bit to 1 maps the I/O registers into $d000-dfff, otherwise the character ROM is selected. Note that if you want to access the I/O registers, both P0 and P1 must not be 0 simultaneously.
P3: Cassette data.
P4: Cassette sense. 0 = PLAY button pressed.
P5: Cassette motor. 0 = motor spins (only if $0192 (cassette motor control flag) is not 0).

If you set both P0 and P1 to 0, the I/O ports will be deactivated.

Here you can find the 6502/6510 instruction set as well as the illegal opcodes.

[1] 64 intern, Data Becker 1983, pp.303-306
[2] 64'er Hardware-Buch, p.25
[3] AFAIR I once verified that by swapping 6510 and 8500.

Updated: November 24th, 1997
Created: January 30th, 1997
Status : Verified on September 1st, 1997