VIC-II (6567 / 6569 / 8562 / 8565) Signal Description ----------------------------------------------------- Pin(s) Signal Dir Description 1-7 D6-D0 in / out Data bus. 8 /IRQ out Interrupt ReQuest. This pin is going LOW when an interrupt was toggled in the VIC-II. There are four possible sources for an IRQ: * rasterline * lightpen * sprite-sprite collision * sprite-background collision 9 LP in LightPen. A falling edge on this input causes an interrupt. 10 /CS in Chip Select. HIGH=VIC-II is decoupled from bus. 11 R/-W in Read/-Write. LOW=write to registers, HIGH=read from registers. 12 BA out ReaDY. When going LOW, the CPU waits after next read cycle for this line going HIGH again. 13 Vdd - Reference voltage. This pin is connected to +12V DC (6567/69), or +9V DC (8562/65). 14 COLOR out Color output. 15 S/LUM out Sync / Lumimance output. 16 AEC out Address Enable Control. Directly connected with AEC of the CPU. When going LOW, the CPU puts its bus lines into high impedance state and is thus totally decoupled from the rest of the system, so that the VIC-II can take control over it. 17 ø 0* out Phi 0. The VIC-II outputs the system clock for the 6510. 18 RAS out Row Address Strobe. 19 CAS out Cow Address Strobe. 20 GND - GrouND. (0V) 21 ø color* in Phi color. The color clock for the VIC-II. 14.31818 MHz for NTSC, 17.734472 MHz for PAL. 21 ø in* in Phi in. DOT CLOCK for the VIC-II. 8.18 MHz for NTSC, 7.88 MHz for PAL. 23 A11 in / out Bit 11 of video Address bus. 24-29 A0/A8-A5/A13 in / out Multiplexed video Address bus. 30-34 A6-A10 in / out Bits 6-10 of video Address bus. 35-38 D11-D8 in / out Color RAM data bus. 39 D7 in / out Bit 7 of Data bus. 40 Vcc - Supply voltage (+5V DC). * The 'ø' is used as Greek 'phi' here. Author: Marc-Jano Knopp on 98/2/18 Source: http://mjk.c64.org