CPU 7501 / 8501

Employed in: C264 series

The 7501/8501 CPU (Central Processing Unit) (or MPU (Micro Processing Unit?)) is an 8-bit processor for the Plus/4, C16, and C116. AFAIK, it is fully compatible with the 6510. It differs only in that is has no NMI and a 8-bit port instead of the usual 6-bit port.

Technical data

1.76MHz [1] (two different clock speeds?)
8 bit data bus
16 bit address bus
8 bit I/O port

Pinout

         +-----__-----+
phi0 in -| 1       40 |- /RES
    RDY -| 2       39 |- R/-W
   /IRQ -| 3       38 |- D0
    AEC -| 4       37 |- D1
    Vcc -| 5       36 |- D2
     A0 -| 6       35 |- D3
     A1 -| 7       34 |- D4
     A2 -| 8       33 |- D5
     A3 -| 9       32 |- D6
     A4 -| 10      31 |- D7
     A5 -| 11      30 |- P0
     A6 -| 12      29 |- P1
     A7 -| 13      28 |- P2
     A8 -| 14      27 |- P3
     A9 -| 15      26 |- P4
    A10 -| 16      25 |- P6
    A11 -| 17      24 |- P7
    A12 -| 18      23 |- Gate IN
    A13 -| 19      22 |- A15
    GND -| 20      21 |- A14
         +------------+

Signal Description

(Click here for ASCII version)

Pin(s) Signal Dir Description
1 ø 0 in^* in Phi 0 in. The system clock signal, which is generated by the TED in the plus/4, C16, and C116, is applied to this input. In these machines, it is about 1.76 MHz (not 100% sure).
2 RDY in ReaDY. When going LOW, the CPU waits after next read cycle for this line going HIGH again.^**
3 /IRQ in Interrupt ReQuest. When going LOW, the CPU loads the PC with the value stored in $fffe / $ffff after processing the current command. This procedure will be executed only when interrupts have been enabled (bit 2 in flag register = 0).
Note that the IRQ signal must be applied until the CPU has checked this pin; a short IRQ pulse is not sufficient [2]. ^**
In the plus/4, C16, C116, there are the following possible sources for an IRQ:

TED
ACIA (plus/4 only)
Expansion port, pin 4

4 AEC in Address Enable Control. When going LOW, the CPU puts its bus lines into high-impedance state and is thus totally decoupled from the rest of the system, so that another chip can take control over it.
5 V_cc - Supply voltage. This pin is connected to +5V DC.
6
7
8
9
10
11
12
13
14
15
16
17
18
19 A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
in / out Address bus. The CPU applies the address of the next datum to be read or written.
20 GND - GrouND. (0V)
21
22 A14
A15 in / out Address bus. The CPU applies the address of the next datum to be read or written.
23 Gate IN in Connected to MUX from TED. For memory management?
24
25
26
27
28
29
30 P7
P6
P4
P3
P2
P1
P0
in / out Processor Port. With these lines, you can control RAM / ROM switching and the Datassette. See below (Programming info) for details.
31
32
33
34
35
36
37
38
D7
D6
D5
D4
D3
D2
D1
D0
in / out Data bus.
38 R/-W out Read/-Write. With this line, the CPU controls whether the next DRAM access will be a read or write cycle. LOW=write, HIGH=read. Note that all accesses only take place when ø2 is HIGH.^**
39 ø2 out^* out Phi2 out. The CPU outputs the system clock for the rest of the chips for synchronization.
40 /RES in RESet. When going LOW, the CPU resets and waits for a LOW-HIGH transistion to load the PC with the value stored in $fffc/$fffd. After power-up, the NE555 pulls this line to LOW for a short time and half a second(?) later back to HIGH.

^* The 'ø' is used as Greek 'phi' here.
^** Assumption.

Pin(s)	Signal	Dir	Description
1	ø 0 in^*	in	Phi 0 in. The system clock signal, which is generated by the TED in the plus/4, C16, and C116, is applied to this input. In these machines, it is about 1.76 MHz (not 100% sure).
2	RDY	in	ReaDY. When going LOW, the CPU waits after next read cycle for this line going HIGH again.^**
3	/IRQ	in	Interrupt ReQuest. When going LOW, the CPU loads the PC with the value stored in $fffe / $ffff after processing the current command. This procedure will be executed only when interrupts have been enabled (bit 2 in flag register = 0). Note that the IRQ signal must be applied until the CPU has checked this pin; a short IRQ pulse is not sufficient [2]. ^** In the plus/4, C16, C116, there are the following possible sources for an IRQ: TED ACIA (plus/4 only) Expansion port, pin 4
4	AEC	in	Address Enable Control. When going LOW, the CPU puts its bus lines into high-impedance state and is thus totally decoupled from the rest of the system, so that another chip can take control over it.
5	V_cc	-	Supply voltage. This pin is connected to +5V DC.
6 7 8 9 10 11 12 13 14 15 16 17 18 19	A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13	in / out	Address bus. The CPU applies the address of the next datum to be read or written.
20	GND	-	GrouND. (0V)
21 22	A14 A15	in / out	Address bus. The CPU applies the address of the next datum to be read or written.
23	Gate IN	in	Connected to MUX from TED. For memory management?
24 25 26 27 28 29 30	P7 P6 P4 P3 P2 P1 P0	in / out	Processor Port. With these lines, you can control RAM / ROM switching and the Datassette. See below (Programming info) for details.
31 32 33 34 35 36 37 38	D7 D6 D5 D4 D3 D2 D1 D0	in / out	Data bus.
38	R/-W	out	Read/-Write. With this line, the CPU controls whether the next DRAM access will be a read or write cycle. LOW=write, HIGH=read. Note that all accesses only take place when ø2 is HIGH.^**
39	ø2 out^*	out	Phi2 out. The CPU outputs the system clock for the rest of the chips for synchronization.
40	/RES	in	RESet. When going LOW, the CPU resets and waits for a LOW-HIGH transistion to load the PC with the value stored in `$fffc/$fffd`. After power-up, the NE555 pulls this line to LOW for a short time and half a second(?) later back to HIGH.

Technical info

The 7501 is a derivative of the 6510 and built into the C264 series. The first machines used the 7501, while later Commodore employed the 8501, which is fully compatible.

Programming info

As opposed to the 6502, the 7501 has an integrated 8 bit I/O port, which is used for both the serial bus and controlling the datassette. The Data Direction Register at address $0000 (?) controls whether the Peripheral Data Register port bits at address $0001 (?) are inputs or outputs. If Bit 3 of the Date Direction Register is 1, then Bit 3 of the Peripheral Data Register is configured as output, whereas it would be configured as input if bit 0 in the Data Direction Register was 0. The individual bits of the Peripheral Data Register have the following functions:

P0: SERIAL DATA OUT.
P1: SERIAL CLK output
P2: SERIAL ATN output
P3: Cassette motor.
P4: Cassette read.
P5: Not externally accessible.
P6: SERIAL CLK input
P7: SERIAL DATA input. If jumper J8 is closed, also for Cassette SENSE.

Here you can find the 6502/6510 instruction set as well as the illegal opcodes, which are AFAIK are identical to the 6510 illegal opcodes.

[1] Plus/4 Bedienungshandbuch
[2] C16 Bedienungshandbuch

Updated: June 24th, 1998
Created: April 24th, 1998
Status : NOT VERIFIED!