6510 Signal Description
 -----------------------
 
 Pin(s)   Signal     Dir     Description

    1    ø 0 in*     in      Phi 0 in. The system clock signal, which is
                             generated by the VIC-II in the C64, is applied
                             to this input. In the C64, it is about 1MHz.

    2       RDY      in      ReaDY. When going LOW, the CPU waits after
                             next read cycle for this line going HIGH
                             again.

    3      /IRQ      in      Interrupt ReQuest. When going LOW, the CPU
                             loads the PC with the value stored in $fffe /
                             $ffff after processing the current command.
                             This procedure will be executed only when
                             interrupts have been enabled (bit 2 in flag
                             register = 0).
                               Note that the IRQ signal must be applied
                             until the CPU has checked this pin; a short
                             IRQ pulse is not sufficient.
                             In the C64, there are three possible sources
                             for an IRQ:

                                * VIC-II, pin 8 (rasterline, lightpen,
                                  etc.)
                                * CIA #1 (timer)
                                * Expansion port, pin 4

    4      /NMI      in      Non Maskable Interrupt. When going LOW, the
                             CPU loads the PC with the value stored in
                             $fffa / $fffb after processing the current
                             command.
                             In the C64, there are three possible sources
                             for an NMI:

                                * RESTORE key
                                * CIA #2
                                * Expansion port, pin D

    5       AEC      in      Address Enable Control. When going LOW, the
                             CPU puts its bus lines into 'tri-state' [
                             TRANSLATION! ] and is thus totally decoupled
                             from the rest of the system, so that another
                             chip can take control over it.

    6      Vcc        -      Supply voltage. This pin is connected to +5V
                             DC.

  7-20    A0-A13  in / out   Address bus. The CPU applies the address of
                             the next datum to be read or written.

   21      GND        -      GrouND. (0V)

  22-23  A14-A15     out     Address bus. The CPU applies the address of
                             the next datum to be read or written.

  24-29   P5-P0   in / out   Processor Port. With these lines, you can
                             control RAM / ROM switching and the
                             Datassette. See below (Programming info) for
                             details.

  30-37   D7-D0   in / out   Data bus.

   38      R/-W      out     Read/-Write. With this line, the CPU controls
                             whether the next DRAM access will be a read or
                             write cycle. LOW=write, HIGH=read. Note that
                             all accesses only take place when ø2 is HIGH.

   39    ø2 out*     out     Phi2 out. The CPU outputs the system clock for
                             the rest of the chips for synchronization.

   40      /RES      in      RESet. When going LOW, the CPU resets and
                             waits for a LOW-HIGH transistion to load the
                             PC with the value stored in $fffc / $fffd.
                             After power-up, timer A in the NE556 pulls
                             this line to LOW for a short time and half a
                             second later back to HIGH.

* The 'ø' is used as Greek 'phi' here.


Author: Marc-Jano Knopp <mjk@c64.org> on 97/12/17
Source: http://mjk.c64.org